The development of a memory device that includes memory cells disposed three-dimensionally is ongoing. For example, a NAND memory device has a memory cell array with a three-dimensional structure including a plurality of stacked electrode layers and channel layers penetrating the electrode layers in a stacking direction. Different potentials are applied to the plurality of electrode layers, respectively, and the memory cell array is driven by potential differences between the electrode layers and the channel layers. To increase a degree of integration of the memory cell array having such a configuration, it is typically effective to make the electrode layers thinner so as to increase the number of stacked electrode layers and to make the interlayer insulating layers electrically isolating the electrode layers from one another thinner. However,making the electrode layers thinner increases the electrical resistance of the electrode layers, which is disadvantageous, and making the interlayer insulating films thinner disadvantageously increases the parasitic capacitances between the electrode layers. This will cause a delay in operating speed within the memory cell array and possible cause memory cells to malfunction.